Conventionally, an SRAM cell is fabricated by using a planar type MOS field effect transistor (Metal-Oxide-Silicon Field-Effect Transistor) on a bulk type or an SOI (Silicon On Insulator) silicon substrate. However, in near future, it will become difficult to suppress the short channel effect in a bulk planar type MOS field effect transistor, which causes an increase of leakage current. As a method to avoid this problem, Non-Patent Document 1 suggests fabricating an SRAM cell by using a four-terminal double gate FET (Field-Effect Transistor).
This SRAM cell is realized with an area of 118 F2, where F denotes a half length of the pitch of the metallic wiring in the first layer. However, no consideration is taken in this SRAM cell from a view point of reducing standby power consumption. An SRAM cell circuit designed from a point of view of reducing the standby power consumption, the circuit will be, for example, as shown in FIG. 5. In the SRAM cell shown in FIG. 5, the circuit is consisting of NMOS and PMOS four-terminal double gate FETs. Current flowing through the NMOS and PMOS transistors is drastically reduced by raising the threshold voltage by operation of the threshold voltage control gates on standby. However, an area of the SRAM cell becomes more than 160 F2 if the SRAM cell shown in FIG. 5 is implemented in the usual way such as disclosed in Non-Patent Document 1.
This figure cannot satisfy a requirement for realizing a high density integration of SRAM device with small area by using four-terminal double-gate-FET-SRAM cells. Hence, in order to improve the performance of the four-terminal double gate FET SRAM cell, the present inventor proposed a following SRAM cell arrangement in Patent Document 1.
An SRAM cell includes first to fourth semiconductor thin plates standing on a single substrate and sequentially arranged parallel to each other. A first four-terminal double gate FET (M1) with a first conduction type is formed on the first semiconductor thin plate, second and a third four-terminal double gate FETs (M3 and M2) with a second conduction type connected in series to each other are formed on the second semiconductor thin plate, fourth and fifth four-terminal double gate FETs (M6 and M4) with the second conduction type connected in series to each other are formed on the third semiconductor thin plate, and a sixth four-terminal double gate FET (M5) with the first conduction type is formed on the fourth semiconductor thin plate, respectively. The third and fourth four-terminal double gate FETs (M2, M6) constitute select transistors with logic signal input gates connected to a word line, and the first and second four-terminal double gate FETs (M1, M3)and the fifth and sixth four-terminal double gate FETs (M4, M5) respectively constitute cross-coupled complementary inverters to realize a flip-flop. Logic signal input gates of the first and fifth four-terminal double gate FETs (M1, M5) are arranged on the side facing to the second and the third semiconductor thin plates respectively. Threshold voltage control gates of the second and third four-terminal double gate FETs (M3, M2) and threshold voltage control gates of the fourth and fifth four-terminal double gate FETs (M6, M4) are arranged to face to each other, and each of these threshold control gates are connected in common to a first bias wiring. Threshold control gates of the first and sixth double gate FETs (M1, M5) are connected in common to a second bias wiring, and the word line and the first and second bias wirings are arranged in a direction perpendicular to the alignment direction of the first to the fourth semiconductor thin plates.
FIG. 6 is a schematic diagram illustrating a device arrangement method of the SRAM cell disclosed in Patent Document 1. FIG. 7 is a circuit diagram modified corresponding to the arrangement of the SRAM cell.
The SRAM cell arrangement disclosed in Patent Document 1 has following features.
1. Surfaces of the semiconductor thin plates facing with each other on which FETs with the conduction type different from each other are implemented are used as logic signal input gates, thereby enabling to reduce numbers of contacts when contacts are connected to wires in a layer upper than the first layer.
2. Surfaces of the semiconductor thin plates facing with each other on which FETs with the same conduction type are implemented are used as threshold gates, thereby enabling to reduce numbers of contacts when contacts are connected from wires in the upper layers.
3. When a word line WL is arranged in a direction perpendicular to the direction of semiconductor thin plates, contacts connected to WL on which a row selection signal is applied are arranged on a straight line, thereby making connection between WL and the contacts efficient.
4. Since the contacts from wires providing a bias to control the threshold voltage are aligned on the straight line parallel with WL, the layout becomes simple, and a row-by-row threshold voltage control synchronized to the change in the voltage on the WL is realized.
5. Since the SRAM cell is arranged repeatedly in a cell array with a translational symmetry to the WL direction, with a line symmetry to the BL direction with respect to a boundary line between the neighboring cells, contacts for power supply voltage VDD, and VSS,, contacts of BL, and BL˜, and gate contacts for the threshold voltage control signal applied to M1 and M5 can be shared between cells.
By providing the above features, the SRAM cell in Patent Document 1 was successful in reducing the SRAM cell area down to 144 F2.
In order to realize an SRAM cell using the four-terminal double gate FETs with smaller area and to realize a highly integrated SRAM device, this figure, however is not sufficient.    Patent Document 1: W02008/081740.    Patent Document 2: W02008/069277.    Non-Patent Document 1: H. Kawasaki et al., “Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond”, 2006 Symposium on VLSI Technology Papers, P. 86-87 (2006).